Data processing apparatus for retrieving information-bearing media



May 9, 1967 D. s. OLIVER 3,319,231

DATA PROCESSING APPARATUS FOR RETRIEVING INFORMATION-BEARING MEDIAOriginal Filed Aug. 17. 1961 12 heets-Sheet l J (D 52 a g 8 I I I E a g'5 I P0 0 LLI l o o 3 Q a fi \n: rw 3, 5 2 l. 2 Z O 9.0) 2 u 2 I-Z -D ou t CE 6 m 8 38 0: 0 u 0. 8 n:

o m t o 1- s l g m E Q 2 DONALD $.OLIVER 1: 4 g i INVENTOR. BY

ATTORNEY.

May 9. 1967 D. s. OLIVER DATA PROCESSING APPARATUS FOR RETRIEVINGINFORMATION-BEARING MEDIA Original Filed Aug. 17, 1961 l2 heets-SheetDONALD S. OLIVER GAPWIDT ll 1 INVENTOR ATTORNEY.

May 9. 1967 D s OLIVER 3, ,231

DATA PROCESSING APPARATUS FOR EETHIEVING INFORMATION-BEARING MEDIAOriginal Filed Aug. 17, 1961 12 Sheets-Sheet 4 [ll L l l H DONALD S.OLIVER INVENTOR.

BY QMa/QM ATTORNEY.

D. S. OLIVER DATA PROCESSING APPARATUS FOR RETRIEVINGINFORMATION-BEARING MEDIA 1961 May 9. 1967 12 Sheets-Sheet 0 OriginalFiled Aug. 17,

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ATTORNEY.

May 9, 1967 D. s. OLIVER 3,319,231

DATA PROCESSING APPARATUS FOR RETRIEVING INFORMATTON -BEARING MEDIAOriginal Filed Aug. 17, 1961 l2 heet5-$heet DONALD S. OLEVER INVENTOR.

ATTORNEY.

May 9. 1967 D. s. OLIVER 3,31

DATA PROCESSING APPARATUS FOR RETRIEVING INFORMATION-BEARING MEDIAOriginal Filed Aug. 17, 1961 12 Sheets-Sheet w 268 OUTPUT COINCIDENCEFIG.|2

DONALD S. OLIVER INVENTOR.

BY A4.

ATTORNEY.

FIG. 8

FIG. 8

FIG ll May 9. 1967 Original Filed Aug. 17. 1961 D. s. OLIVER 3,319,231

DATA PROCESSING APPARATUS FOR RETRIEVING INFORMATION-BEARING MEDIA lheets-Sheet v DONALD $.OLJVER INVENTOR ATTORNEY May 9, 1967 D. s. OLIVERDATA PROCESSING APPARATUS FOR RETRIEVING INFORMATIONBEARING MEDIA 1961l2 Sheets-Sheet 10 Original Filed Aug 17,

INVENTOR.

DONALD S.OLIVER ATTORNE K May 9, 1967 D. s. OLIVER DATA PROCESSINGAPPARATUS FOR RETRTEVING INFORMATION-BEARING MEDIA 1961 12 Sheets-Sheet1L Original Filed Aug. 17,

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BY iOau (i? M R Wm PM 0 E V S m D L A N O D 0 wwm wmm ATTORNEY.

May 9, 1967 D. s. OLIVER DATA PROCESSING APPARATUS FOR RETRIEVINGINFORMATION-BEARING MEDIA 1961 12 Sheets-Sheet 12 Original Filed Aug.17,

DONALD S. OLIVER INVENTOR.

x I, BY WQM ATTORNEY.

United States Patent Ofiice 3 ,3 l 9,23 l Patented May 9, 1 967 wareContinuation of application Ser. No. 132,141, Aug. 17, 1961. Thisapplication Nov. 4, 1965, Ser. No. 513,630

7 Claims. (Cl. 340172.5)

This application is a continuation of my United States application, Ser.No. 132,141, filed Aug. 17, 1961, and assigned to the same assignee asthe present invention.

The present invention relates to data processing. More particularly, theinvention relates to data processing systems for transporting, locating,segregating, retrieving and reading of data bearing media. Moreespecially, the invention relates to a data processing circuit forsensing and processing identification code data indicia carried bygraphic data bearing cards or chips, such as photographic cards orchips. The term data bearing medium or media as used herein includesdata bearing bodies, such as film chips, cards and sheets, and the framecarriers to support the bodies. The term further includes such bodiesintegrally formed with a carrier means.

In a copending application filed by Donald S. Oliver, entitled, MagneticData Processing, filed Apr. 12, 1960, Ser. No. 21,754, now abandoned, adata processing system is described. The present invention presents animprovement over that apparatus. In another copending application filedby Donald S. Oliver entitled, Data Processing Device, filed on the samedate herewith, an improvement in the sensing device is presentedenabling serial read-out of identification code signals. In the earlierfiled Oliver apparatus, a data bearing medium such as a film chip,photographic transparency or positive, cooperates with a guide transportsystem which slidably engages and supports the medium at an obliqueangle. The media are preferably propelled under the influence of theflow of air.

In order to identify a given medium and program a desired path oftransport, for purposes of selection, retrieval, recycling, etc., eachmedium is identification coded with a data code preferably magneticallyrecorded. A magnetic striping in this system is applied either to a filmchip, or a carrier frame for the film chip, coplanar with the plane ofthe medium. The striping is recorded transversely and polarized acrossthe face of the striping or magnetic tape. The polarization ispreferably perpendicular to an edge of a rectangular medium. Fringefields extend from the medium at the edge. The recording thus providesrecorded data indicia which are linearly disposed at discrete intervals.Since the identification code can be polarized either with a north polefield fringing from the edge of the medium or with a south pole fieldfringing from the edge, a positive signal indicative of the presence ofbinary information is obtainable. In the event that a signal below apredetermined threshold value appears in the interval sensed, the mediumis assumed to be defective in structure and/or function and is extractedfrom the system.

As noted above, the normal plane of a medium is at an oblique anglerelative to its direction of motion. In the co-pending Oliver apparatus,a magnetically edgecoded chip is transported at an angle past amulti-channel magnetic sensing means. The means includes a number ofindividual heads which are disposed correspond ing with the position ofan identification code indicium interval.

all)

In contrast with the earlier filed Oliver apparatus, the presentinvention is distinguishable in that linearly disposed data indicia arereceived in sequence, thus eliminating the requirement of a plurality ofparallel input circuits.

It is desirable to determine the presence of a data bearing media, senseits identification code, verify the code as a true signal and decidewhether the particular medium has to be acted on in accordance with apreselected program.

In a typical application, a data bearing medium is in motion wtihrespect to a sensing head. In the prior art, a reference signal iscompared with an input signal within a given time interval. For the mostgeneral applica tion, however, the velocity of the medium relative tothe sensing head is subject to considerable variation. Furthermore, therate at which media may be read is limited by the time requirement for agiven reading. In contrast with the above, the data processing circuitof the present invention enables the recognition of a desired signalwithout regard to time. The present system thus operates to provideidentification code recognition Without unduly limiting thecharacteristic of signals with which it can operate.

It is therefore an object of the invention to provide an improved dataprocessing circuit.

It is further the object of the invention to provide an improved dataprocessing circuit for data bearing media carrying identification codedata and indicia.

Another object of the invention is to provide an improved dataprocessing circuit for determining the presence of a data bearingmedium. Still another object of the invention is to provide an improveddata processing circuit enabling rapid read-out from a data bearingmedium in motion.

Still another object of the invention is to provide an improved dataprocessing circuit enabling the recognition of an identification codefrom data indicia carried by graphic data bearing media.

Yet another object of the invention is to provide an improved dataprocessing circuit characterized by simplicity of structure and ease ofoperation.

A further object of the invention is to provide an improved dataprocessing circuit for data bearing media having magnetically recordedidentification code data indicia.

Still another object of the invention is to provide an improved dataprocessing circuit for rapid, efiicient and accurate processing ofmagnetically recorded identification code data indicia carried by databearing media.

In accordance with the invention, there is provided a data processingcircuit. The circuit includes a receiver means for receiving a sequenceof discrete signals. The receiver means includes a reference means forproviding a preselected signal of a predetermined number of referencepulses. Comparator means are coupled to the receiver and reference meansfor comparing successive signals and reference pulses. In this manner, acomparator signal is produced in accordance with a difference in aselected characteristic between successive signals and reference pulses.Counting means are coupled to the receiver means for producing acounting signal in accordance with the number of discrete signals.Control means are coupled to the comparator and counting means forproducing a control signal in response to the counting and comparatorsignals.

In one form of the invention, the discrete signals are derived frommagnetically recorded, linearly disposed identification code dataindicia. In another form of the invention, the received signals arediscrete pulses and are compared, pulse for pulse, with the referencepulses. The

comparator means produces a difference signal only in response to thefirst difference in a selected characteristic between a received signaland its corresponding reference pulse. The control means produces acontrol signal only if the number of received signals compared is thesame as the predetermined number of reference pulses, and no differencesignal is derived from the comparator.

Other and further objects of the invention will be apparent from thefollowing description of the invention taken with reference to theaccompanying drawings.

In the drawings:

FIG. 1 is a schematic diagram of a data processing system embodying thepresent invention;

FIG. 2 is an enlarged, schematic, partially perspective view of amagnetic sensing head used in accordance with the invention;

FIG. 3 is a plan view of a data bearing medium useful in a dataprocessing system embodying the present invention;

FIG. 4 is an enlarged, fragmentary, partially schematic perspective viewof a magnetic tape-bearing, data bearing medium useful in accordancewith the invention;

FIG. 5 is a schematic block diagram of a data processing circuitembodying the invention;

FIG. 6 is a graph of voltages associated with the circuit of FIG. 7;

FIGS. 7A and 7B are a detailed, schematic block diagram of a dataprocessing circuit embodying the invention;

FIG. 8 is a detailed, schematic circuit diagram of the discrete signalssensing and pulses circuit in FIG. 7A;

FIG. 9 is a detailed, schematic circuit diagram of the comparator,mismatch memory and coincidence circuits in FIG. 7A;

FIG. 10 is a detailed, schematic, circuit diagram of the countersynchronizing trigger pulses circuit in FIG. 7A;

FIG. 11 is a detailed, schematic, circuit diagram of the shift andrequested number registers and reference pulses circuits in FIG. 7B;

FIG. 12 is a detailed, schematic, circuit diagram of the photoelectricpresence sensing, reset and interrogate pulses circuits of FIG. 7B;

FIG. 13 is a detailed, schematic, circuit diagram of the discretesignals memory and dropout circuits of FIG. 7A.

Background and description of the invention The invention is concernedwith data processing involving the ordering, presentation and use ofdata in various physical forms including graphic data, and the systems,methods, apparatus and devices for handling data bearing media carryingvisually presented or graphic information, as well as abstract digitalor analogue information for use in machines. Of particular concern isthe handling of discrete information elements such as film cards or filmchips. Such data processing systems require techniques for converting aninformtaion file into discrete elements, transporting each such discreteelement from a file to a point of detection, than to a point ofswitching and finally to a point of readout, either visually or bymachine.

The invention includes methods and apparatus for handling smallunmounted film chips as well as larger sections of film called hereinfilm cards" to distinguish them from the small unmounted film chips."The handling of the larger film cards in data media preferably involvesa supporting carrier frame in addition to the film in itself. The frameis used as a carrier and can therefore carry a number of types of databearing media.

The chip or car-d may provide its own support or carrier means.

Data bearing cards, aperture cards or punched cards, for example, can beused equally well as a carrier for photographic film chips. The filmcards may be coded to provide inherent control of a selection,distribution, recycling etc. For various applications, magnetic coding,

optical coding, and mechanical coding, such as provided by notches, areuseful. A magnetic striping adjacent an edge of a carrier or databearing body is highly desirable for edge scanning to identify a desiredmedium rapidly. Since a photograph contains an enormous amount ofinformation per unit area, it is frequently desirable to utilize opticalcoding on the face of a data bearing body or its carrier combined withmagnetic and mechanical coding adjacent an edge.

Sections of guide panels have guide tracks to receive a data bearingmedium such as a film card and carrier frame. The medium is propelledalong the track channels and is normally inclined at an angle ofapproximately to the track. The medium is free to move in eitherdirection along the track channels. A number of media may be stacked ina section of track channels. Each medium may be driven along the tracksby an air stream. In this manner there is no problem with frictionbetween the surfaces of film cards mounted on adjacent carriers. For agiven system, sections of track are joined for various functions. Meansmay be provided for trapping and holding an individual medium.

The medium is transported to and stored in various types of bins, eachof which includes a basic section of track. The bins may be permanentlymounted or movable. The bins are so constructed as securely to hold themedia in place. The bin is adapted for insertion into an automaticsystem with, for example, air stream propulsion or for insertion into amanually controlled handling unit for use as a local file.

While it is normally desirable to transport media oriented at an anglerelative to the track, for many purposes it is necessary to move or holdthe medium in its own plane. Special sections of track can be providedto convert the orientation of the medium from inclined plane motion tomotion in its own plane or any angle in between. For static viewing,contact printing or readout, a selected medium may be trapped and heldor moved in its own plane for viewing of its various parts.

Recirculation may be obtained by combining selected sections of trackand properly directing fluid drive means to provide, for example, asuitable air stream operative at all points along a desired path. Theability to merge or intermix cards is incorporated in the recirculationsystem.

Magnetic edge coding greatly enhances the speed and ease with which anindividual medium may be identified and selected. A strip offerro-magnetic material is attached along the surface of the mediumadjacent to an edge. Magnetic coding is provided by recording signalshaving relative positive or negative magnetic polarity at right anglesto the edge. The code can be edge'sensed while the medium is moving athigh speed and at an angle. A magnetic sensing head may be located incoupling proximity with media moving in a section of track. Thepreferred coding system used herein requires a definite signal above adesired threshold. Absence of such a definite magnetic signal indicatesa defect and produces rejection of the medium. The present systemcontemplates the use of a serial readout which greatly simplifies therelated coincidence logic circuitry.

Principles of operation In the prior art a number of systems have beenproposed that use an angularly oriented magnetic sensing gap withrespect to the direction of motion of a magnetically recorded tape andparticularly with respect to the surface of the tape disposed adjacentthe gap. The present invention is distinguishable from these devices inthat linearly disposed discrete information is serially read out by amagnetic sensing head with the gap width disposed at an angle withrespect to the linear disposition of the data.

In the case of magnetic recording, as a magnetically recorded indiciummoves past a gap in a magnetic sensing head, its field produces a fluxwhich links with the sensing head winding. A voltage is induced in thewindings 1n proportion to the time rate of change of the flux linkingthe winding. The amplitude of the voltage generated 13 unaffected by therelative location of the passing magnetic bit with respect to itsdisposition along the width of the head gap. Thus a single wide gap headmay be used to sense a plurality of magnetically recorded indicia bymeans of serial read-out. The disposition of each indicium with respectto the line of the gap width, or sensing axis, in no way affects theamplitude of the voltage output of the sensing head. The voltage outputof the head corresponds with the amplitude and polarity of a magneticindicium. Thus, the polarity of a discrete electrical signal isdetermined by the polarity of the recorded signal. In the event that nosignal is present, this indicates a defect.

The motion of the magnetic tape past a magnetic sensing head produces achange in the magnetic flux circuit to include the magnetic path in thehead. This in turn produces the excitation of a surrounding windingwhich produces an electrical signal. This output voltage is eitherpositive or negative to produce a positive or negative signal indicativeof a binary code. In accordance with such a code, for example, 0 mayimply a positive pulse and 1 may imply a negative pulse.

The linear display of information is readily applied longitudinallyalong the edge of a magnetic tape. Reading planar data bearing media byexposing an edge of the medium to a sensing head is superior to facereading the medium. It enables, for example, ready scanning of aplurality of media in rapid etfieient sequence.

In the present invention, then, linearly disposed discrete informationindicia are moved past a sensing head at an angle relative to a sensingaxis. The sensing head produces a sequence of discrete signals. Thesignals may be discrete, for example, in the sense that a givencharacteristic such as polarity successively changes. This change mayonly be apparent with respect to a given receiver input sensitivitythreshold. Thus, a conventional sine wave in this sense provides asequence of discrete signals with respect, for example, to polarity.

An input program is selected for in turn selecting a specific databearing medium with regard to a specific function. In order to recognizea desired medium, a preselected sequence of a predetermined number ofreference pulses is provided in accordance with a desired program. Thereceived discrete signals in sequence are compared, signal for pulse,with the reference pulses. For complete coincidence, indicating thepresence of a desired medium, the input signals and reference pulsesmust agree, for example, in polarity. As soon as a difference inpolarity is indicated, the medium is rejected as not being the desiredone.

In the event that there is complete agreement signal for pulse, anindication that this medium is indeed the desired medium takes place.Note that comparison takes place independent of time. As each receivedsignal comes along, it is compared with the next reference pulse insuccession. The comparator, however, only looks for mismatches.

In the application involving magnetically recorded identification codedata indicia, the signals are magnetically polarized to provide anoutput electrical signal of an electrical polarity corresponding withmagnetic polarity. That is to say, a north magnetic pole, for example,may correspond with a positive electrical voltage amplitude, and a southmagnetic pole may correspond with a negative electrical voltageamplitude. The absence of a signal from the medium indicates a defect.

The true signal verification and insurance against spurious signalstakes place in two major steps. A photoelectric sensing element, forexample, may sense the presence of a medium, enabling the comparison,counting and control functions. After the medium passes the photoelec-6. tric sensor, these functions may be disabled. True signalverification thus takes place by virtue of a determination as to thepresence of the medium, enabling the comparison, counting and controlfunctions only during the presence of the medium. Additionally, thereceived signals are counted to insure the correct number as comparedwith a predetermined number of reference pulses. In the event that themedium interrogated provides less than the predetermined number ofsignals, the medium is extracted from the system.

Explanation and description of the data processing device in FIGS. 1-4

Referring now to the drawings, and with particular reference to FIGURE1, there is here illustrated a data processing device embodying theinvention.

The device as illustrated generally comprises a transport means coupledto a sorting means for propelling and distributing data bearing media.The sorting means is in turn coupled to storage bins or other desiredpaths. The sorting means is also coupled back to the transport means forrecycling. The transport and sorting means generally comprise an openguide system. Coupled t0 the guide system along the path of a databearing medium is a magnetic sensing means. The head is coupled to arecognition means including a coincidence logic circuit which derives aninput from a programmer. The output of the logic circuit is coupled to acontrol circuit which in turn is coupled to a switching device. Theswitching device is coupled to the sorter for directing selected mediaalong selected predetermined paths.

Thus referring to FIG. 1 there is here illustrated a data processingdevice generally indicated at 10. The device includes an open guidesystem having a transport means 11 coupled to a sorting means 12. A databearing medium 13 is shown guided at an oblique angle relative to itsdirection of travel. The data bearing medium 13 has a pair of extensiontab means 14 and 15 engaging a pair of spaced parallel track channels 16and 17 which are formed in a supporting panel 18. A magnetic sensinghead 19 is shown coupled to the guide path adjacent an edge of a movingmedium 13. The head includes a sensing gap 20 presenting a sensing axis.As will be more fully described below, the head basically comprisesferro-magnetic material formed in the shape of an incomplete loop whichdefines a gap. The width of the gap presents a sensing axisperpendicular to the direction of motion of the medium 13. There is anangle between the plane of the medium 13 and the line of the width ofthe gap 20 or the sensing axis. The head 19 is coupled to a recognitionmeans 21 including a coincidence logic circuit. Coupled to therecognition means is a programmer 22. The means 21 are coupled to acontrol circuit 23 which in turn is coupled to a switching means 24. Theswitching means is coupled in controlling relation to the sorter 12. Thesorter 12 is coupled to the input of the transport means 11 forrecycling purposes. The sorter is also coupled to a plurality of storagebins 25, 26, 27 and 28. The bins as shown are indicated as beingnumbered from 1 through N implying that an arbitrary number of bins areuseful in the present device.

In FIG. 2 the relative orientation of the data bearing medium 13 to theline of the gap width 20, the sensingaxis, is shown. As indicated inFIG. 2, the medium 13 is oriented at an angle A with respect to thesensing axis defined by the gap 20 and moves past the gap length L. Thesensing head 19 includes a magnetic core 29 surrounded by an inductivewinding 30 from which an output voltage V is derived. The output voltageV generally has the form indicated at 31 or 32 depending upon thepolarity of the magnetically recorded signal. The curves 31 and 32represent signal amplitude V taken against a time base 2.

In FIGURE 3 two of the many forms of data bearing media useful with thepresent invention are shown. FIG. 3(a) presents a data bearing medium ofthe type used with four spaced track channels formed in a pair ofparallel supporting panels. Here the medium generally indicated at 33has a carrier frame 34 which carries a film card or chip 35. Along oneedge of the frame and substantially co-planar with the frame and chip isa magnetic striping 36. The magnetic striping 36 carries magneticallyrecorded identification code indicia 37. The film chip or card 35carries data in various graphic forms.

The indicia 37 are linearly disposed along an edge of the medium 33 asshown. The magnetic recording and hence the polarized magnetic signalsare transverse to the longitudinal direction of the magnetic striping.The carrier is affixed to a pair of cylindrical rods providing tabextensions 38, 39, 40 and 41. The extensions are adapted for engagementwith a system of track channels for guiding the medium along a desiredpath. The channels are characteristically so spaced as to cause themedium to assume an orientation at an angle relative to the track aswell as relative to the direction of travel.

If the medium 33 were to move past the gap with the linearly disposedindicia parallel to the sensing axis, the single wide gap sensing headwould only see a net differential fiux which would produce in its outputa signal representative of the integrated effect of the individuaimagnetic bits. In order to obtain serial readout the medium must beoriented in such a manner as to provide the line of indicia at an anglewith respect to the sensing axis. Each indicium is disposed at discreteintervals so chosen with respect to the orientation angle A as toprovide isolated indicium, i.e. an isolated signal for readout at agiven time.

In FIG. 3(1)) :1 data bearing medium adapted for use with track rails isshown. Here a medium generally indicated at 42 is shown. The medium 42includes a carrier 43 and film chip or card 44 supported by the carrierframe 43. The carrier frame is so formed as to provide a system of fournotches 45, 46, 47 and 48 in opposed pairs in spaced relation. Themedium is thus adapted for engagement with a system of parallel, spacedtrack rails which support the medium by engagement with the notches.Again the spacing between the rails is such as to support the medium atan angle relative to its direction of motion. Along an edge of themedium is a magnetic striping 49 with linearly disposed identificationcode indicia 50.

While the media in FIG. 3 illustrates the identification code stripingapplied to the frame, it will be apparent that the code may be appliedto an integrally formed film chip or card which provides its own supportor carrier. In such a case the film chip or card is so formed as toprovide either notches or tab extensions for guidance along track railsor track channels respectively.

Referring now to FIG. 4, there is here illustrated an enlargedfragmentary view of a preferred embodiment of the magnetic stripingsection of the data bearing medium 33. In this view the magnetic fluxlines are schematically illustrated. Each digit of the identificationcode is separated by a discrete interval bounded by dashed lines asshown. The ferro-magnetic material is carefully magnetized at spaceddiscrete intervals to minimize intercoupling.

FIG. 4 particularly shows the magnetic striping 36 which carries theindicia linearly disposed at discrete intervals. Each identificationcode indicium is recorded transversely of the magnetic striping ormagnetic tape. Such a tape is typically formed of a plastic carrier withan iron oxide suspension. The well known magnetic tape may be used forthis purpose.

Referring to the individual indicium as a magnetic bit, the polarity ofeach bit is indicated in the drawing. The code as shown indicates abinary identification number 1000-], for example. The bits between digit4 and digit N are not shown.

Each magnetic bit may be viewed as an individual bar magnet. The dashline simply indicates the effective boundary region for the fringe fieldoutside the magnet. The encoding takes place in such a manner as toprovide a planar magnetic indicia bit with flux lines transverse withthe length of the striping. The bit produces flux lines which emanatefrom the pole in opposite directions out of the plane of the medium. Itwill be observed for example that the polarity of the second hit isreversed and the fringe fields are directed oppositely from the fieldsrelating to the first magnetic bit.

Operation Referring to FIG. 1, a data bearing medium with anidentification code of linearly disposed magnetically recorded indiciais introduced to the transport means and propelled, for example, by airflow. A program for directing the media along the desired path isintroduced in the programmer 22. This instruction is applied to therecognition means 21. The recognition means 21 includes a coincidencelogic circuit which receives, stores and compares the information withthe instruction from the programmer. The output of the recognition isapplied to a control circuit 23. The control circuit may be a relaysystem which controls or actuates the switching means 24. The switchingmeans by, for example, obstructing or clearing a track channel or trackrail, directs a media along a desired path. In the sorter 12 the mediaare directed to any of a number of storage bins 25, 26, 27 or 28 or to arecycling path to go through this system again. In addition to thestorage functions, the individual medi um may be extracted from thesystem for viewing or other purposes or directed along other paths.

Description and explanation of the circuit in FIG. 5

Referring now to FIG. 5, there is here illustrated a schematic blockdiagram of a data processing circuit embodying the invention. Thediagram generally includes a receiver means having a reference means forproviding a preselected sequence of a predetermined number of referencepulses. A comparator is coupled to the receiver and reference pulsegenerator. The output of the comparator is applied through a mismatchmemory circuit to a control circuit. A discrete signals counter iscoupled to the output of a discrete signals sensing head and amplifierand to a control device. A photoelectric sensing means or detectorcircuit is coupled to the counter circuit and to the control circuit.The control circuit derives an input from the comparator, counter, andphotoelectric circuits.

Referring now in detail to the drawing, discrete signals are received bya discrete signals sensing head 101 which is coupled to an amplifier102. An input request is applied to a reference pulse generator 103. Theoutputs of the amplifier 102 and generator 103 are coupled to acomparator 104. An output of the amplifier 102 is coupled to a counter105. An output of the counter 105 is coupled to a discrete signalsmemory 106. Another output of the counter 105 is applied to thegenerator 103. The output of the comparator 104 is coupled to a mismatchmemory circuit 107. The memories 106 and 107 are coupled to elements ofa control circuit having a coincidence gate circuit 108 and dropout gatecircuit 109. A photoelectric sensing head 110 is optically coupled to adata bearing medium. The head 110 is coupled to medium presence signalamplifier 111. An output of the amplifier 111 is coupled to a resettrigger circuit 112 and another output is coupled to an interrogatetrigger circuit 113. The reset circuit 112 is coupled to the counter105, the mismatch memory 107 and the discrete signals memory 106. Anoutput of the interrogate circuit 113 is coupled to the coincidencecircuit 108 and the dropout circuit 109.

A data bearing medium of the type illustrated in FIG. 3 in the manner ofthe system in FIG. 1 moves past discrete signals sensing head 101. Theoutput of the head 101 is a series of discrete signals, such as pulsesof suceessive polarity, and is applied to the amplifier 102. An inputrequest, for example, for selecting a desired medium, is applied to thereference pulses generator 103. The discrete signal pulses from theamplifier 102 and reference pulses from the generator 103 are comparedfor polarity differences in the comparator 104. In the event of a singledifference, an output signal is derived from the comparator 104 andapplied to the mismatch memory circuit 107.

The photoelectric sensing head 110 detects the presence of a medium, forexample, by the interruption of a light beam. The output of the head 110is amplified in the circuit 111. The leading edge of, for example, apulse indicating the presence of the medium, is applied to the resetcircuit 112 which produces a reset trigger pulse. The trigger pulse fromthe circuit 112 restores the counter 105 to zero and resets thegenerator 103 for producing a new sequence of reference pulses. Thereset trigger also neutralizes the mismatch memory 107 and discretesignals memory 106. A short time later an interrogate trigger pulse fromthe circuit 113 enables the coincidence circuit 108 and the dropout gatecircuit 109.

The discrete signal pulses are coupled from the amplifier 102 to thecomparator 104 and compared there on a pulse for pulse basis withreference pulses derived from the generator 103. The coincidence circuit108 is disabled in response to a difference signal from the mismatchmemory 107. The counter 105 produces an indication of the desired countwhich is stored in the discrete signals memory circuit 106. When theindication of a desired number of pulses is stored in the memory 106, anenabling signal is applied to the coincidence circuit 108. Thecoincidence circuit is thus enabled by a signal indicating the desirednumber of pulses from the memory circuit 106, and an interrogate triggerfrom the circuit 113. The first indication of a mismatch from the memorycircuit 107 disables the coincidence circuit. The output of the circuit108 is a control signal indicating the presence of a desired medium forselection for a desired function. In the system of FIG. 1, this impliesthat it may be selected for retrieval from the system or placed inposition for viewing or copying.

The dropout gate circuit 109 produces a control signal which extracts amedium from the system where a defect or malfunction is indicated. Thisindication is provided by the absence of a counter signal indicating thedesired number of received discrete signal pulses.

Broadly speaking, the system operates to extract a defective ormalfunctioning medium from the system, recirculate a medium as not beingthe desired one for selection or selects a desired medium for furtheroperation. The coincidence circuit provides a comparison between a givenmedium identification code data indicia with a requested number. If themedium number is coincident with the requested number a coincidencesignal is generated. As the medium passes the magnetic reading head,magnetically recorded binary indentification code indicia on the mediumgenerate a series of positive and negative pulses in the output of themagnetic reading head. These pulses are amplified and fed into thecomparator circuit. The reference pulse generator or requested numberregister stores the requested number in parallel form. A magnetic pulsecounter cooperates with the register to feed reference pulses in serialform and in synchronism with the received discrete pulses. Any mismatchwhich occurs as a result of the pulse for pulse comparison is stored asa difference signal in the mismatch memory. The desired pulse sequenceis stored in the discrete signal memory.

A photoelectric detector or sensing head is used to sense the presenceof a medium passing the magnetic sensing head. The leading edge of thepulse from the photocell is used to generate a reset trigger pulse forresetting the counter and the memory. The trailing edge of the pulse isused to generate an interrogate pulse which enables the coincidence anddropout circuits. The dropout circuit operates in such a manner as totend to extract a medium from the system unless it is disabled by anindication of a proper number of discrete signals plus an indicationfrom the interrogate trigger of the presence of a medium. Thecoincidence circuit, on the other hand, normally produces no outputunless it is enabled by the nth discrete signal and the interrogatetrigger. In the event the circuit 108 is disabled by a signal from themismatch circuit, no output from the coincidence circuit is possible.

In FIGS. 6, 7A and 7B, and in particular FIG. 6, there is illustrated aseries of curves associated with the operation of the circuit in FIG. 7.Case I, the coincidence condition, is illustrated in 6(A). In FIG. 6(A),the curve (a) is the amplified and clipped output pulse of the amplifier138. The pulse may have a duration typically of the order of 5milliseconds. The curve (b) illustrates the reset trigger pulse outputof the reset AND circuit 142; the curve (c) illustrates the outputdiscrete signals of the sensing head 101; the curve (d) illustrates theoutput of the discrete signals P pulses circuit 117; the curve (e), theoutput of the N pulses circuit 116; the curve (f), the output countingpulses of the counter OR circuit 127; the curve (g), the output of thenth pulse memory circuit 134; the curve (h), the output of the referenceP pulses circuit 132; the curve (i), the N pulses circuit 131; the curve(j), the output of the comparator inverter 120a; the curve (k), theoutput of the mismatch memory 121; the curve (l), the interrogatetrigger pulse output of the interrogate inverter circuit 1400; the curve(m), the output of the coincidence NAND circuit 122 and the curve (It),the output of the dropout NAND circuit 135.

Description and explanation of the circuit in FIGS. 7A and B Referringnow to FIGURES 7A and B, there is here illustrated a detailed schematicblock diagram of the data processing circuit in FIG. 5. Magnetic mediumsignals 114 are coupled to the magnetic discrete signals sensing head101 as described above. The output of the head 101 is coupled to theamplifier 102. An output of the amplifier 102 is coupled to a discretesignals inverter 115 and thence to a discrete signals N pulses circuit116. Another output of the amplifier 102 is directly coupled to discretesignals P pulses circuit 117. The output of the circuit 116 is directlycoupled to a comparator AND circuit 118 and the output of the circuit117 is directly coupled to a second comparator AND circuit 119. Thecircuits 118 and 119 are coupled to a comparator OR circuit 120 which isin turn coupled to a mismatch memory, flip-flop circuit 121. The outputof the flip-flop or memory circuit is coupled to a coincidence ANDcircuit 122.

The counting circuit is broadly derived, in the present embodiment, froma magnetic shift register. Another pair of outputs from the circuits 116and 117 are coupled directly to counter AND circuits 124 and 123,respectively. Still other outputs of the circuits 116 and 117 areapplied to counter inverter circuits 125 and 126. The outputs of thecircuits 123 and 124 are coupled to a counter 0R circuit 127. Thecircuit 127 is coupled to a counter shift pulse driver 128 which is inturn coupled to a magnetic shift register circuit 129. A requestednumber register 130 is coupled to the shift register to provide adesired sequence of reference pulses. The outputs of the register 129,as shown, are numbered 1, 2, 3, and n. Each output is coupled to one oftwo reference pulses circuits 131 and 132. The circuit 131 responds onlyto binary N s and the circuit 132 only to binary P s. The circuits 131and 132 are coupled to the comparator AND circuits 118 and 119,respectively. The nth output of the register 129 is coupled to a countertrigger circuit 133. The output of the circuit 133 is coupled to adiscrete signals memory flip-flop circuit 134. An output of the memorycircuit 134 is coupled to the coin- 11 cidence AND circuit 122 andanother output is coupled to a dropout AND circuit 135.

A data bearing medium 136 optically coupled to a photoelectric detector137, the output of which is coupled to a photoelectric presence pulseamplifier 138. The output of the amplifier 138 is applied to aphotoelectric presence pulse shaping circuit 139. An output of thecircuit 139 is directly coupled to a trigger AND circuit 140. Anotheroutput of the circuit 139 is coupled through an inverter circuit 141 tothe circuit 140. Still other outputs of the circuit 139 are coupleddirectly to an interrogate AND circuit 142, and through an interrogateinverter circuit 143 to the circuit 142. The output of the circuit 142is coupled to a reset pulse driver circuit 144 which is in turn coupledto the register 129. The circuit is coupled to the discrete signalsmemory circuit 134, and to the mismatch memory circuit 121. Theinterrogate circuit 140 is coupled to the dropout AND circuit 135 andthe coincidence AND circuit 122.

System logic In the system associated with FIGURES 7A and B and thewaveforms of FIGURE 6, the received discrete signals are identified bythe presence of a positive or negative voltage amplitude. Thus, the termP represents a received discrete binary signal having a positive voltagerelative to ground as measured across an input signal sensing head, themagnetic sensing head 201. The magnitude of the voltage is greater thana given threshold level. The symbol N represents a negative receivedbinary signal.

The received signals are compared with stored binary reference pulses toprovide an indication of coincidence. The reference pulses are definedas requested numbers or reference pulses P and N The operations of therelated logical circuits are described by binary "1 and notation. Inthis sense the binary "1 indicates the presence of a signal, and thebinary "0," the absence of a signal. The corresponding electricalvoltage levels relative to ground are zero volts for the binary 0, and anegative voltage, for example, l2 volts, for the binary "1.

A logical AND" circuit has a plurality of input and one outputterminals. Such a circuit operates to provide a binary 1 in its outputif and only if binary ls are applied to all inputs. Thus, for two inputterminals, if a binary "0 appears at either or both inputs, a binary "0"appears at the output. If and only if a binary "1 appears at bothinputs, a binary "1" appears at the output.

A logical OR circuit for binary 1s" operates to produce a binary 1" inits output if it receives a binary 1" in either one or both of theinputs. A binary 0 is produced at the output if and only if binary 0sappear at all of the inputs.

In logical notation the negative of an AND circuit is a NAND circuit. ANAND circuit for binary ls operates to produce in its output a binary 0"if and only if binary ls are applied at the input. In such a circuit thepresence of a binary 0" in any or all of the inputs produces a binary 1in the output. Noting that binary "1 or 0 indicates the presence orabsence of a signal, the signal itself may be inverted. Thus, a signalrepresented by P is a binary "1 and the signal represented by F is aninverted binary 1." A logical NAND circuit for binary 0s" operates toproduce a binary l in its output if and only if binary 0's appear at allof the inputs. If a binary 1 appears at any or all of the inputs, abinary "0" is produced at the output.

A NOR circuit is the negative of an OR" circuit. A NOR" circuit forbinary ls operates to produce a binary 0" in the output if a binary 1 ispresent at any or all inputs. A binary "1 is produced at the output ifand only if binary 0s" appear at all inputs. In electrical terms ifnegative supply voltage is applied at any or all inputs of a NORcircuit, the output in the preferred embodiment is 0 volt. If 0 volt areapplied at all of the inputs, the output is the negative supply voltage.

The OR circuit and the AND circuit may be converted into a NOR and aNAND circuit, respectively, by serially coupling an inverter circuit tothe output. The inverter inverts a binary "0 to produce a binary 1 andvice versa. In electrical terms a 0 voltage input is converted into anegative supply voltage output. Conversely, a negative supply voltageinput is converted into a 0 voltage output.

The circuits to be described below involving the logical operationsdescribed above include: the comparator and coincidence circuits; thediscrete signals impulse memory and dropout; and the discrete signalpulse counter. The existence of a received discrete signal and theinterrogate, reset, coincidence and drop-out states are represented by abinary "1. The absence of the above mentioned signal or state isrepresented by a binary 0."

Operation Magnetic signals 114 are coupled by the motion of a databearing medium carrying identification code data indicia to the magneticdiscrete signals sensing head 101, and the amplifier 102. The output ofthe amplifier 102 is directly coupled to a circuit 117 such as a Schmitttrigger circuit. Another output of the amplifier 102 is applied througha discrete signals inverter circuit 115 to the circuit 116. The originalsignal as shown at the input of the circuit 117 has successively apositive voltage amplitude, two negatives and a positive corresponding,for example, with the binary identification code number N P P N Thecircuit 117 operates to produce an output of positive going pulsescorresponding with the P s in the original signal. The other output ofthe amplifier 102 is inverted to provide in the output of the circuit116 positive going pulses corresponding with the original N s. Thus, theoutput of the circuit 116 provides binary N s to the comparator ANDcircuit 118, and the output of the circuit 117 provides is to thecomparator AND circuit 119.

The comparator AND circuits 118 and 119 operate in such a manner as toproduce no output unless a mismatch occurs between received discretepulses and reference pulses, i.e., between the requested number and thatof a given medium interrogated. If either circuits 118 and 119 producesan output indicative of a mismatch, the OR circuit 120 produces adifference signal to trigger the mismatch memory flip-fiop circuit 121.A single signal is enough to trigger the mismatch memory circuit 121 andmaintain an output mismatch or difference signal until the circuit isreset. The mismatch signal disables the coincidence AND circuit 122,i.e., prevents it from producing a coincidence signal in its output.

The comparator AND circuit 118 produces an output signal in response toreceived N 's and reference P s. The circuit 119 responds to received Ps and reference N s. In the event of a mismatch one of the circuitsproduces an output mismatch or difference signal. The mismatch signal iscoupled through the OR circuit 120 to the mismatch memory 121.

The shift register and counter circuits operate cooperatively in such amanner as to produce both reference pulses and an indication of thecount or number of discrete pulses. The AND circuit 118 derives inputreference P s from the shift P reference pulses circuit 132; the circuit119 derives input reference N s from the reference N circuit 131.

An output of the comparator circuit 116 is coupled directly to a NANDcircuit 124 and through inverter circuit 126 to the circuit 124.Similarly, an output of the signals 13 circuit 117 is coupled directlyto a NAND circuit 123 and through an inverter 125 to the circuit 123.Since there is a time delay through the inverter, the AND circuitproduces an output trigger having a pulse width equal to the time delaythrough the inverter.

These pulses in the output of the circuits 123 and 124 are coupled tothe NOR circuit 127. The circuit 127 produces in its output a series ofcounting pulses which are all positive going. The counting pulses areapplied to the counter shift pulse driver circuit 128, which producesamplified pulses which are applied to the magnetic shift register 129.The magnetic shift register, as will be described in greater detailbelow, operates in such a manner as to produce a first output in the #1output channel which then shifts to produce an output for the #2channel, etc, through the nth channel. The shift register circuit isalways set up so that it produces a negative amplitude pulse in itsoutput shifted in time relative to the previous pulse. The requestednumber, as indicated here, N P P N is obtained by setting the requestednumber register to switch the inputs of one or the other of thereference circuits 132 and 131, which produces the corresponding P s orN s in the output.

The output of the circuit 131 corresponds with the P s in the originalsignal and the output of the 132 corresponds with N s. Thus, therequested number is obtained by switching the output of the magneticshift register to the proper trigger 131 or 132. The T from the circuit132 are compared with the N s from the circuit 116 at the comparator ANDcircuit 118. The 1 s from the trigger circuit 131 are compared with theP s from the comparator circuit 117 at the AND circuit 119. As notedabove, a diiference or mismatch between the received discrete signalsand the requested number reference pulses cause the OR circuit 120 toproduce in its output a signal indicative of the mismatch. This signalis applied to the mismatch memory 121 which produces a disabling signalfor coincidence AND circuit 122.

The photoelectric detector 137 senses the presence of the data bearingmedium 136 and produces a voltage output which is coupled to theamplifier 138. The output of the amplifier 138 is applied to thephotoelectric shaping circuit 139 which produces in its output anegative going square wave pulse. The negative pulse and an inverteddelayed pulse from inverter 141 are compared at the interrogate ANDcircuit 140 to provide an output interrogate trigger pulse having thewidth of the time delay provided by the inverter circuit 141.

The reset trigger pulse is amplified at the driver circuit 144 andapplied to the magnetic shift register to restore the count to zero. Thereset pulse is also applied to the discrete signal pulse memory 121 toclear it for the new indication of a desired signal count. The resettrigger is also coupled to the mismatch memory circuit 121 to clear it.

The positive-going pulse output of the trigger circuit 139 is coupleddirectly to the reset AND circuit 142 and through the reset invertercircuit 143 to the circuit 142. The circuit 142 produces in its output adelayed reset pulse corresponding with the leading edge of the outputpulse from the trigger circuit 139, as opposed to the output of theinterrogate trigger circuit 140, which corresponds with the trailingedge. The interrogate pulse enables the coincidence AND circuit 122 andthe dropout AND circuit 135. The requested number is obtained byswitching the output of the magnetic shift register as indicated above,to correspond with the number of a desired data bearing medium. The nthpulse output of the register 129 produces in the output of the nthsignal pulse circuit 133 a pulse to trigger the nth signal pulse memorycircuit 134. The positive-going output of the circuit 134 is applied toenable the coincidence AND circuit 122, as noted above, and the negativeoutput is applied to disable the dropout AND circuit 135.

14 Description and explanation of the trigger circuit of the discretesignal and amplifier circuits in FIG. 8

Referring now to FIG. 8, there is here illustrated a detailed schematiccircuit diagram of the sensing head, the amplifier circuit, the invertercircuit and the triggers corresponding with the input trigger circuit inFIG. 7. Here a magnetic sensing head is coupled through a capacitor to athree-stage transistor amplifier circuit providing a gain ofapproximately 40 to 45 db. The output of the amplifier is coupledthrough a single stage transistor inverter circuit to a dual transistormonostable trigger circuit.

Thus the winding of a magnetic sensing head 201 is coupled through acapacitor 202 to the base of the first amplifier stage transistor 203.The other two stages are associated with transistors 204 and 205. Thus,PNP type transistors 203, 204 and 205 have their emitter connected tobias resistors 206, 207 and 208 respectively. The other end of theresistors are connected together to the positive side of a power supply,for example, a twelve volt supply.

Resistors 209, 210 and 211 are connected between the bases andcollectors of transistors 203, 204 and 205, respectively. The transistorcollectors are connected together to the negative supply. The powersupply may consist of a center tap grounded direct current batterysupply with positive and negative terminals. In the preferredembodiment, two twelve volt batteries connected in series with theircommon terminals junction grounded provide an adequate source of supply.The collectors of each of the transistors 203, 204 and 205 are coupledthrough capacitors 215, 216 and 217, respectively, to the base of thenext succeeding transistor. The capacitor 217 is coupled to the base ofa transistor 218 connected in an inverter circuit. A resistor 219 isconnected between the collector and base of the transistor 218. Thecollector is connected through a load resistor 220 to the negativesupply. The emitter is connected through a load resistor 221 to thepositive supply. The collector is coupled through a capacitor 222 to thebase of a transistor 223. The transistor 234 and the transistor 223 areconnected in a monostable trigger circuit. The emitter of the transistor218 is coupled through a capacitor 224 to the base of a transistor 225.A transistor 235 and the transistor 225 are connected in a monostabletrigger circuit.

The bases of the transistors 223 and 225 are connected through resistors226 and 227 to ground. The emitters are connected through bias resistors228 and 229 to ground. The collectors are connected through loadresistors 230 and 231 to the negative supply. The collectors oftransistors 223 and 231 are also connected to output terminals marked Band A, respectively. The collectors are connected through resistors 236and 237 to the bases of the complementing transistors 234 and 235,respectively. The collectors of the transistors 234 and 235 areconnected through resistors 232 and 233 to the negative supply. Theemitters of the transistors 234 and 235 are connected to the emitters ofthe transistors 223 and 235, respectively. The resistors 23-6 and 237are connected in series with resistors 238 and 239, respectively, to thepositive side of the supply.

The trigger circuit including the transistors 223 and 234 correspondswith the comparator monostable trigger circuit 116 in FIG. 7. Thecircuit including transistors 225 and 235 corresponds with the circuit117 in FIG. 7.

Operation The output of the sensing head 201 is coupled through thecapacitor 202 to the base of the transistor 203. The transistors 203,204 and 205 are connected in a threestage amplifier circuit to provide,e.g., of the order of 40 to 45 db. gain. The amplified output of thetransistor 205 is applied to the inverter circuit associated with thetransistor 218. The inverter is coupled to a pair of comparatormonostable trigger circuits corresponding to the circuits 116 and 117 inFIG. 7. One trigger circuit provides only discrete binary N s" forcoupling to the comparator, mismatch and coincidence circuits; the otherprovides only P s."

A received, amplified signal pulse applied to the base of the invertertransistor 218 provides an output of one polarity across the collectorload resistor 220. The collector is coupled through the capacitor 222 tothe base of the transistor trigger circuit 223. A pulse of the oppositepolarity is developed across the load resistor 221 and is coupledthrough the capacitor 224 to the base of the transistor 225.

The transistor 234 of the trigger circuit is normally conducting throughone resistor 228 to produce a negative voltage at the emitter of thetransistor 223. The base of the transistor 223 is thus positive relativeto the emitter and maintains the transistor 223 cut off. The

bias voltage developed between the base and emitter of the transistor223 may, for example, be the order of one volt. Positive pulsesappearing at the base of the transistor 223 have no eflect on thecircuit. A negative pulse however, in excess of one volt, drives thebase of the transistor 223 negative relative to its emitter and causesthe transistor to conduct heavily. The collector of 223 is normally atnegative supply voltage, e.g., 12 volts. When transistor 223 is turnedon, the voltage at its collector goes in a positive direction toward 0.A positive voltage is developed across the resistor 236 at the base ofthe transistor 234 to cut it oh. This produces a positive-going pulseappearing in the output of transistor 223. When a negative pulse at thebase of the transistor 223 passes, the base goes positive tending to cutoff the transistor 223, restore its collector to negative supply voltageand enable the transistor 234 to conduct. The conduction current throughthe transistor 234 maintains the transistor 223 out off until the nextpulse of suflicient amplitude appears at its base.

It follows that the circuit operates to ignore all but the signalsexceeding the input threshold bias voltage. This tends to insure truesignal operation and filter out other voltage variations.

The monostable trigger circuit for supplying binary P s is a circuitwhich is complementary in operation to the circuits described. Thiscircuit is associated with the transistors 225 and 235. Here, thetransistor 225 is normally maintained at out off by virtue of thecurrent drawn by the transistor 235 through the resistor 229. Thetransistor 235 is normally maintained at a negative bias voltagerelative to its emitter to maintain it in conduction. The triggercircuit again operates in such a manner as to ignore positive pulses atthe base of the transistor 225 and responds only to negative pulses. Thenegative pulse on the base of the transistor 225 which exceeds the biasvoltage between the base and emitter, causes it to conduct heavily andcut off the transistor 235 in the same manner as described above withregard to the transistors 223 and 234.

It follows that one of the trigger circuits produces an output signalpulse for each input pulse of a given polarity. Because of the inverson,the 223, 234 circuit provides only binary signals corresponding, e.g.,to original N s. The 225, 235 circuit provides only binary signalscorresponding, e.g., to original P s."

Description and explanation of the mismatch, comparator and coincidencecircuits in FIG. 9

Referring now to FIGURE 9, there is here illustrated the detailedschematic circuit diagram of the Mismatch Comparator and Coincidencecircuits outlined in FIG. 7. The AND circuits associated with a pair oftransistors 242 and 247 correspond with the circuits 119 and 118,respectively, in FIG. 7. The OR circuit 120 in FIG. 7 corresponds withthe circuit of transistors 252 and 256; the mismatch memory 121corresponds with the circuits of a pair of transistors 260 and 264. Thecoincidence AND circuit 122 corresponds with the circuit formed with atransistor 268. A pair of resistors 240 and 241 are connected in commonto the base of the transistor 242. The base is also connected through aresistor 243 to the positive supply. The emitter of the transistor 242is grounded and the collector is connected through a load resistor 244to the negative supply. A pair of resistors 245 and 246 are connected incommon to the base of transistor 247. In a manner similar to the circuitabove, the base of the transistor 247 is connected through a resistor248 to the positive supply, and the collector is connected through aresistor 249 to the negative supply. The emitter is grounded. Thecollectors are coupled through resistors 250 and 251 to the base oftransistor 252.

The base of the transistor 252 is connected through a resistor 253 tothe positive supply; the collector is connected through a resistor 254to the negative supply, and the emitter is grounded. The collector iscoupled through a resistor 255 to the base of a transistor 256.

The base of the transistor 256 is connected through a resistor 257 tothe positive supply, the collector through a resistor 258 to thenegative supply and the emitter is grounded. The collector is coupledthrough a resistor 259 to the base of transistor 260. The base of thetransistor 260 is coupled through a resistor 261 to the positive supply,the collector is connected through a resistor 262 to the negativesupply, and the emitter is grounded. The collector of 260 is alsocoupled through a resistor 263 to the base of a transistor 264. Thetransistors 260 and 264 and their associated circuitry comprise abistable flipflop" circuit.

The collector of the transistor 264 is connected through a resistor 265to the negative power. The collector is also connected through aresistor 266 to the base of the transistor 260. The junction between thecollector of the transistor 264 and the resistor 266 is connectedthrough a resistor 267 to the base of a grounded emitter connectedtransistor 268. The resistors 269 and 270 are connected together incommon with the resistor 267 to the base of the transistor 268. The baseof the transistor 268 is connected through the resistor 271 to thepositive battery terminal. The collector of the transistor 268 isconnected through a resistor 272 to negative power and the emitter isgrounded. The collector of the transistor 268 is connected to a terminalK which carries the coincidence AND circuit output signal. The base ofthe transistor 264 is also connected through a resistor 273 to positivepower and a resistor 274 to a terminal marked G.

The signal inputs derived at the terminals A, B, D, E, G, H, and I maybe determined from the detailed schematic block diagram of FIG. 7. Moreparticularly, the inputs to terminals A and B are derived from terminalsA and B of FIG. 8; terminals D and E from FIG. 11; terminals G and Hfrom FIG. 12; and terminal I from FIG. 13.

The voltages at terminals A, B, D, and E are normally -12 volts to applya negative bias to the transistors 242 and 249 to cause thesetransistors normally to conduct. With these transistors normallyconducting, a positive voltage is developed at the base of thetransistor 252 across the resistors 250 and 251. The transistors 252 isnormally cut off. Its collector negative voltage is coupled to the baseof the transistor 256 to render it conductive. Its collectorpositive-going voltage is coupled to the base of the transistor 260normally to cut it off. The negative voltage at the collector of 260 iscoupled to the base of the transistor 264 to cause it to conduct. Thepositive voltage developed at its collector is coupled through theresistor 266 to the base of the transistor 260 to hold that transistorcut off.

Terminal H is at negative supply voltage for a no presence signalcondition. The base of transistor 268 is :negative, and the transistorconducting; the voltage at the

1. A DATA PROCESSING SYSTEM COMPRISING: (A) A PLURALITY OF DATA BEARINGMEDIA EACH HAVING A BLOCK OF N BITS OF IDENTIFICATION DATA WHEREIN EACHBIT HAS AT LEAST TWO POSSIBLE VALUES AND WHERE N IS A PREDETERMINEDINTEGER; (B) A SOURCE OF ADDRESS DATA FOR PRODUCING A BLOCK OF N BITS OFADDRESS DATA; (C) READING MEANS FOR READING SAID BLOCK OF N BITS OFIDENTIFICATION DATA OFF OF SAID DATA BEARING MEDIA; (D) COUNTING MEANSCOUPLED TO SAID READING MEANS FOR PRODUCING A FULL COUNT INDICATION IF APARTICULAR BLOCK OF IDENTIFICATION DATA READ BY SAID READING MEANSCONTAINS N BITS OF ADEQUATELY MANIFESTED IDENTIFICATION DATA; (E) ACOMPARATOR FOR COMPARING A PARTICULAR BLOCK OF ADDRESS DATA PRODUCED BYSAID ADDRESS DATA SOURCE WITH A PARTICULAR BLOCK OF IDENTIFICATION DATAPRODUCED BY SAID READING MEANS AND FOR PRODUCING A MATCH INDICATION IFEQUALITY EXISTS BETWEEN SAID PARTICULAR BLOCK OF ADDRESS DATA AND SAIDPARTICULAR BLOCK OF IDENTIFICATION DATA; (F) CONTROL MEANS COUPLED TOSAID COUNTING MEANS AND SAID COMPARATOR INCLUDING SELECTION INDICATINGMEANS FOR PRODUCING A SELECTION COMMAND OUTPUT SIGNAL IF SAID COUNTINGMEANS PRODUCES SAID FULL COUNT INDICATION AND SAID COMPARATOR PRODUCESSAID MATCH INDICATION, TOGETHER WITH REJECTION INDICATING MEANS FORPRODUCING A MEDIA REJECTION CONTROL SIGNAL IF SAID COUNTING MEANS DOESNOT PRODUCE SAID FULL COUNT INDICATION.